Key Features
* Details how the new standard allows for increased portability across tools.
* Covers related standards, including the Numeric Synthesis Package and the Synthesis Operability Package, demonstrating how they can be used for digital systems design.
* Presents four extensive case studies to demonstrate and combine features of the language taught across multiple chapters.
* Requires only a minimal background in programming, making it an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD.
Description
Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs.
VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools.
This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals.
The Designer's Guide to VHDL, 2nd Edition
1 Fundamental Concepts
1.1 Modeling Digital Systems
1.2 Domains and Levels of Modeling
1.3 Modeling Languages
1.4 VHDL Modeling Concepts
1.5 Learning a New Language: Lexical Elements and Syntax
Exercises
2 Scalar Data Types and Operations
2.1 Constants and Variables
2.2 Scalar Types
2.3 Type Classification
2.4 Attributes of Scalar Types
2.5 Expressions and Operators
Exercises
3 Sequential Statements
3.1 If Statements
3.2 Case Statements
3.3 Null Statements
3.4 Loop Statements
3.5 Assertion and Report Statements
Exercises
4 Composite Data Types and Operations
4.1 Arrays
4.2 Unconstrained Array Types
4.3 Array Operations and Referencing
4.4 Records
Exercises
5 Basic Modeling Constructs
5.1 Entity Declarations
5.2 Architecture Bodies
5.3 Behavioral Descriptions
5.4 Structural Descriptions
5.5 Design Processing
Exercises
6 Case Study: A Pipelined Multiplier Accumulator
6.1 Algorithm Outline
6.2 A Behavioral Model
6.3 A Register-Transfer-Level Model
Exercises
7 Subprograms
7.1 Procedures
7.2 Procedure Parameters
7.3 Concurrent Procedure Call Statements
7.4 Functions
7.5 Overloading
7.6 Visibility of Declarations
Exercises
8 Packages and Use Clauses
8.1 Package Declarations
8.2 Package Bodies
8.3 Use Clauses
8.4 The Predefined Package Standard
8.5 IEEE Standard Packages
Exercises
9 Aliases
9.1 Aliases for Data Objects
9.2 Aliases for Non-Data Items
Exercises
10 Case Study: A Bit-Vector Arithmetic Package
10.1 The Package Interface
10.2 The Package Body
10.3 An ALU Using the Arithmetic Package
Exercises
11 Resolved Signals
11.1 Basic Resolved Signals
11.2 IEEE Std_Logic_1164 Resolved Subtypes
11.3 Resolved Signals and Ports
11.4 Resolved Signal Parameters
Exercises
12 Generic Constants
12.1 Parameterizing Behavior
12.2 Parameterizing Structure
Exercises
13 Components and Configurations
13.1 Components
13.2 Configuring Component Instances
13.3 Configuration Specifications
Exercises
14 Generate Statements
14.1 Generating Iterative Structures
14.2 Conditionally Generating Structures
14.3 Configuration of Generate Statements
Exercises
15 Case Study: The DLX Computer System
15.1 Overview of the DLX CP
15.2 A Behavioral Model
15.3 Testing the Behavioral Model
15.4 A Register-Transfer-Level Model
15.5 Testing the Register-Transfer-Level Model
Exercises
16 Guards and Blocks
16.1 Guarded Signals and Disconnection
16.2 Blocks and Guarded Signal Assignment
16.3 Using Blocks for Structural Modularity
Exercises
17 Access Types and Abstract Data Types
17.1 Access Types
17.2 Linked Data Structures
17.3 Abstract Data Types Using Packages
Exercises
18 Files and Input/Output
18.1 Files
18.2 The Package Textio
Exercises
19 Case Study: Queuing Networks
19.1 Queuing Network Concepts
19.2 Queuing Network Modules
19.3 A Queuing Network for a Disk System
Exercises
20 Attributes and Groups
20.1 Predefined Attributes
20.2 User-Defined Attributes
Exercises
21 Miscellaneous Topics
21.1 Buffer and Linkage Ports
21.2 Conversion Functions in Association Lists
21.3 Postponed Processes
21.4 Shared Variables
Exercises
A Synthesis
A.1 Use of Data Types
A.2 Interpretation of Standard Logic Values
A.3 Modeling Combinatorial Logic
A.4 Modeling Sequential Logic
A.5 VHDL Modeling Restrictions
B The Predefined Package Standard
C IEEE Standard Packages
C.1 Std_Logic_1164 Multiv-Value Logic System
C.2 Standard 1076.3 VHDL Synthesis Packages
C.3 Standard 1076.2 VHDL Mathematical Packages
D Related Standards
D.1 IEEE VHDL Standards
D.2 Other Design Automation Standards
E VHDL Syntax
E.1 Design File
E.2 Library Unit Declarations
E.3 Declarations and Specifications
E.4 Type Definitions
E.5 Concurrent Statements
E.6 Sequential Statements
E.7 Interfaces and Associations
E.8 Expressions
F Differences
G Answers to Exercises
References
Index
