RISC System/6000 PowerPC System Architecture

RISC System/6000 PowerPC System Architecture, 1st Edition

RISC System/6000 PowerPC System Architecture, 1st Edition,ISBN9781558603448

Morgan Kaufmann



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Offers support for a wide range of products for the RISC System/6000
product line and AIX operating system, including Uni-processor (UP) and
Symmetric Multiple Processor (SMP) systems. Provides important information
for building many system features such as memory controllers with caches
and bus-to-bus bridges. RISC System/ 6000 PowerPC System Architecture
defines an architecture that allows each operating system--in particular,
the AIX operating system--to run unchanged on all systems that comply with
this architecture. It provides a consistent software interface across a
broad range of system implementations and offers all hardware/software
dependencies necessary for a successful system identification,
configuration and performance tuning process.

An important reference for all programmers and product development
engineers who are developing software and hardware products for the
RISC/System 6000 PowerPC systems. Also useful for system programmers
involved in operating system design, system integrators building products
and parts for the system family, and anyone interested in porting other
operating systems to the RISC System/6000 family.

RISC System/6000 PowerPC System Architecture, 1st Edition

RISC System/6000: PowerPC System Architecture

by International Business Machines, Inc.

    List of Figures

    List of Tables


    Chapter 1 Introduction
      1.1 Memory Architecture

      1.2 Definition of Terms
        1.2.1 Reserved

        1.2.2 Reserved/Unimplemented

        1.2.3 Addressing Notation

        1.2.4 Symbolic Notation

      1.3 Reliability, Availability, and Serviceability (RAS)

    Chapter 2 PowerPC Processor Architecture
      2.1 PowerPC Implementation Specific User's Manual
        2.1.1 Processor Requirements

        2.1.2 Hardware I/O Design Instruction Support Requirements

    Chapter 3 Architected system Memory Map
      3.1 Memory Map Layout

      3.2 Architected System Registers
        3.2.1 Physical Identifier Initialization (PIDI) Register

        3.2.2 Connectivity Configuration Register

        3.2.3 Connectivity Reset Register

        3.2.4 time of Day Registers

        3.2.5 System Reset count Register

        3.2.6 Power/Keylock Status Register (PKSR)

        3.2.7 Software Power on Reset Control Register

        3.2.8 Software Power Off Control Register

        3.2.9 System Specific System Registers

      3.3 Architected System Interrupt Registers
        3.3.1 Data Storage Interrupt Error Register (DSIER)

        3.3.2 SMP Early Power Off Warning (EPOW) External Interrupt Vector Register (XIVR)

        3.3.3 IPLCB/Global Queue Interrupt Routing Mask Location Interface

    Chapter 4 Bring-Up and Configuration Architecture
      4.1 Device Configuration Architecture
        4.1.1 Hardware Architecture Assumptions and Requirements

      4.2 Configuration Registers
        4.2.1 Configuration Sequence

        4.2.2 Architected Configuration Registers

        4.2.3 Architected Configuration Registers Address Map

        4.2.4 Device Specific Configuration Registers

      4.3 Feature ROM Scan (FRS) Architecture
        4.3.1 Address Range

        4.3.2 Criteria for Required ROM

        4.3.3 ROM Type Attributes

    Chapter 5 NVRAM Contents and Mapping
      5.1 NVRAM Usage
        5.1.1 ROM Specific Areas and Their Management

        5.1.2 OCS/SP Implementations

        5.1.3 Non-OCS Implementations

    Chapter 6 Bus Unit Controller (BUC) Architecture
      6.1 BUC Addressing
        6.1.1 Addressing with T=0 (Memory Mapped or Ordinary Segments)

        6.1.2 Addressing with T=1 (Direct-Store Segments)

        6.1.3 Load and Store Addressing Model

        6.1.4 BUC Translation Control Entry (TCE)

        6.1.5 BUC TCE Address Register

      6.2 BUC Interrupt Structure
        6.2.1 BUC Interrupt Scenario

        6.2.2 External Interrupt Vector Register (XIVR)

        6.2.3 End of Interrupt (EOI) Command

      6.3 BUC Data Consistency and Ordering Requirements

    Chapter 7 IOCC Architecture
      7.1 System Structure
        7.1.1 Virtual Memory

        7.1.2 System memory

        7.1.3 Bus Memory and Bus I/O Address Space

        7.1.4 IOCC Facilities

      7.2 Bit and Byte Numbering Conventions
        7.2.1 Big-Endian and Little-Endian Mode Concurrency

        7.2.2 Two Processor Implementations of Little-Endian Mode

        7.2.3 I/O Load and Store Access from the Processor to the I/O

        7.2.4 DMA Data Interchange Between I/o and Memory

      7.3 Micro Channel Bus Protocols
        7.3.1 Micro Channel Arbitration

        7.3.2 Basic Transfer Cycle

        7.3.3 Micro Channel Buys Errors

        7.3.4 Exception Reporting and Handling

        7.3.5 Micro Channel Interrupts

      7.4 IOCC Programming Model
        7.4.1 Load and Store Instructions

        7.4.2 Bus Master

        7.4.3 DMA Slave

        7.4.4 IOCC Commands

        7.4.5 IOCC Registers

        7.4.6 IOCC Interrupt Structure

        7.4.7 Non-Recoverable Errors

        7.4.8 Recoverable Errors

    Chapter 8 System Resources
      8.1 Operator Interface
        8.1.1 Display Interface

        8.1.2 IPL/Operation Mode

        8.1.3 Operator Reset

      8.2 Non-Volatile Random Access Memory (NVRAM)

      8.3 Time Facilities
        8.3.1 Time of Day Clock

        8.3.2 Time Base Enable

        8.3.3 Symmetric Multi-Processor (SMP) Synchronization

    Chapter 9 External Interrupt Architecture
      9.1 External Interrupt Overview
        9.1.1 System Level Interrupt Register Overview

        9.1.2 Interrupt Routing Layer

        9.1.3 Interrupt Presentation Layer

      9.2 Interrupt Register Definition Details
        9.2.1 External Interrupt Request Register (XIRR)

        9.2.2 Current Processor Priority Register (CPPR)

        9.2.3 External Interrupt Source Register (XISR)

        9.2.4 Queued Interrupt Request Register (QIRR)

        9.2.5 Most Favored Request Register (MFRR)

        9.2.6 Global Queue Interrupt Request Register (G_QIRR)

        9.2.7 SMP Global Queue Interrupt Routing Masks (GQ_IRMs)

        9.2.8 Available Processor Mask (APM)

    Chapter 10 System Exception Processing
      10.1 Exception Handling
        10.1.1 Target Market Categories

        10.1.2 Interrupts and Checkstop

        10.1.3 Exception Conditions

        10.1.4 Processor Designs

        10.1.5 BUC Designs

        10.1.6 Real Address Mmemory Mapped I/O

        10.1.7 Multiprocessor

        10.1.8 Diagnostics

        10.1.9 System Exception Support Facilities

        10.1.10 System Exception IPLCB Interface

    Chapter 11 System Bus Architecture
      11.1 60X Bus Overview
        11.1.1 60X Bus Memory Coherence

        11.1.2 60X Bus Transfer Protocols

      11.2 6XX System Bus Overview

    Chapter 12 Bring-Up Function and IPLCB
      12.1 SMP Bring-Up Function

      12.2 IPL Control Block (IPLCB) Interface
        12.2.1 Purpose of the IPLCB

    Chapter 13 Vital Product Data (VPI)
      13.1 VPD Format
        13.1.1 Keyword Definitions

        13.1.2 Device Specific VPD Data Requirements

    Chapter 14 AIX Based Diagnostics Requirements
      14.1 AIX Based Diagnostics Dependencies
        14.1.1 Hardware Dependencies

        14.1.2 Hardware Testing Dependencies

        14.1.3 VPD Requirements from AIX Based Diagnostics

        14.1.4 Maintenance Package Operator Panel Requirements

        14.1.5 Built-in Self-Tests (BISTs)

        14.1.6 Power-On Self-Tests (POSTs)

        14.1.7 Service Processor (SP) Diagnostics

        14.1.8 Built-in Diagnostics and Off-Line Diagnostics

    Appendix A Processor Dependencies
      A.1 Segment Register (SR) or Segment Table Entry (STE) Bits

      A.2 External Interrupt Request Register (XIRR) Latency

      A.3 T=1 Direct-Store Segments

      A.4 Alignment Interrupts

    Appendix B Standard I/O Interface
      B.1 Recommended Mapping

    Appendix C Target Market Categories
      C.1 Exception Handling by Target Market Categories

    Appendix D Memory Controller Example
      D.1 Device ID Register for Memory Controller

      D.2 Device Specific Configuration Registers

      D.3 Error Correction Codes (ECC)

    Appendix E System Exception Implementation Examples
      E.1 RISC/System 6000 Model 250

      E.2 Typical SMP System

      E.3 AIX

      E.4 System Exception Registers
        E.4.1 Memory Controller Status Register (MCSR)

        E.4.2 System Exception Status Register (SESR)

        E.4.3 Memory Error Address Register (MEAR)

        E.4.4 System Exception Address Register (SEAR)

        E.4.5 Time-Out Registers

      E.5 Processing Examples

    Appendix F IPLCB Example
      F.1 IPLCB Structure Definition

      F.2 Notes on IPLCB Front End and IPL Directory Structures
        F.2.1 Memory Allocation and Access Rules for IPLCB

        F.2.2 IPL ROM Arrays

        F.2.3 Per-Processor Scratch Pad Array Structure

        F.2.4 Per-BUC Scratch Pad Array Structure

        F.2.5 Per-Adapter Family 2 Scratch Pad Array Structure

        F.2.6 System Info Scratch Pad

    Appendix G AIX Dependencies on the IPLCB
      G.1 IPLCB/Implementation Dependent Placements

      G.2 Dependencies for PowerPC System Platforms
        G.2.1 Struct ipl_directory

        G.2.2 Struct ipl_info

        G.2.3 Struct iocc_post_results

        G.2.4 Struct ram_data

        G.2.5 Struct net_data

        G.2.6 Struct global_spad

        G.2.7 Struct sga_data

        G.2.8 Additional Dependencies for PowerPC System Platforms

    Appendix H AIX Command and Event Indicators
      H.1 Encoded Messages

      H.2 Event Indicators
        H.2.1 Dump Indicators

        H.2.2 Debugger Indicator

        H.2.3 Boot and Install Indicators

        H.2.4 Diskette Command and Progress Indicators

        H.2.5 Console Indicators

        H.2.6 Diagnostic Controller Event Indicators

        H.2.7 AIX Event Indicators

    Appendix I Power IOCC Arch. vs PowerPC IOCC Architecture
      I.1 Changes from Power IOCC Architecture

    Appendix J 32/64 Bit BUC Arch. Differences & Considerations
      J.1 32-Bit BUCs Versus 64-Bit BUCs

    Appendix K Big-Endian and Little-Endian Tutorial
      K.1 Endian Byte Ordering

      K.2 Structure Mapping Examples
        K.2.1 PowerPC Processor Byte Ordering


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