Cache and Memory Hierarchy Design, 1st Edition

Description

An authoritative book for hardware and software designers. Caches are by far the simplest and most effective mechanism for improving computer performance. This innovative book exposes the characteristics of performance-optimal single and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution times. It presents useful data on the relative performance of a wide spectrum of machines and offers empirical and analytical evaluations of the underlying phenomena. This book will help computer professionals appreciate the impact of caches and enable designers to maximize performance given particular implementation constraints.

Cache and Memory Hierarchy Design, 1st Edition

• Preface


• Symbols


• 1. Introduction


• 2. Background Material
  
  • 2.1. Terminology
  
  
  • 2.2. Previous Cache Studies
  
  
  • 2.3. Analytical Modelling
  
  
  • 2.4. Temporal Analysis in Cache Design
  
  
  • 2.5. Multi-Level Cache Hierarchies


• 3. The Cache Design Problem and Its Solution
  
  • 3.1. Problem Description
  
  
  • 3.2. Two Complementary Approaches
  
  
  • 3.3. Experimental Method
    
    • 3.3.1. The Simulator and Related Infrastructure
    
    
    • 3.3.2. The System Models
    
    
    • 3.3.3. The Input Traces
    
    
    • 3.3.4. Observations, Lessons and Summary
  
  
  • 3.4. Analytical Approach


• 4. Performance-Directed Cache Design
  
  • 4.1. Speed - Size Tradeoffs
  
  
  • 4.2. Speed - Set Size Tradeoffs
  
  
  • 4.3. Block Size - Memory Speed Tradeoffs
    
    • 4.3.1. Optimal Block Size with Cycle Time Degradation
    
    
    • 4.3.2. Independent Block and Fetch Sizes
    
    
    • 4.3.3. Optimal Block Size with Alternate Fetch Strategies
  
  
  • 4.4. Globally Optimum Cache Design


• 5. Multi-Level Cache Hierarchies
  
  • 5.1. Introduction
  
  
  • 5.2. Motivation
  
  
  • 5.3. Intermediate Cache Design
    
    • 5.3.1. Decomposition of the Hierarchy
    
    
    • 5.3.2. Speed - Size Tradeoffs
    
    
    • 5.3.3. Set Size Tradeoffs
    
    
    • 5.3.4. Block Size and Fetch Size Tradeoffs
    
    
    • 5.3.5. Summary
  
  
  • 5.4. Optimal Memory Hierarchy Design
  
  
  • 5.5. A Detailed Example
  
  
  • 5.6. Fundamental Limits to Performance
  
  
  • 5.7. Summary


• 6. Summary, Implications and Conclusions
  
  • 6.1. Summary
  
  
  • 6.2. The Implications of Performance-Directed Cache Design
  
  
  • 6.3. Suggestions for Further Research


• Appendix A. Validation of the Empirical Results
  
  • A.1. The VAX Traces
  
  
  • A.2. The R2000 Traces
  
  
  • A.3. Combining the R2000 and the VAX Results


• Appendix B. Modelling Write Strategy Effects


• References


• Index