ASIC and FPGA Verification, 1st Edition

A Guide to Component Modeling

 
ASIC and FPGA Verification, 1st Edition,Richard Munden,ISBN9780125105811
 
 
 

  

Morgan Kaufmann

9780125105811

9780080475929

336

235 X 191

A valuable resource for anyone who needs to simulate digital designs not contained in a single chip.

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Key Features

*Provides numerous models and a clearly defined methodology for performing board-level simulation.
*Covers the details of modeling for verification of both logic and timing.
*First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.

Description

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today’s digital designs.

ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.

Readership

Digital system designers and industry short courses focused on component modeling

Richard Munden

Affiliations and Expertise

CEO, Free Model Foundry

ASIC and FPGA Verification, 1st Edition

1.Introduction to Board-Level Verification; 2.Tour of a simple model; 3.VHDL packages for component models; 4.Introduction to SDF; 5.Anatomy of a VITAL Model; 6.Modeling Delays; 7.VITAL truth tables; 8.Modeling timing constraints; 9.Modeling registered devices; 10.Conditional delays and timing constraints; 11.Negative timing constraints; 12.Timing Files and Backannotation; 13.Adding Timing to Your RTL Code; 14.Modeling Memories; 15.Considerations for Component Modeling; 16.Modeling Component Centric Features; 17.Testbenches for Component Models

Quotes and reviews

Today it is still very difficult to verify board or larger system designs through simulation or any other technique. This important book addresses the largest ingredient needed to make simulation possible—the availability of integrated circuit component models. Addressed inside is how to use VITAL extensions and other conventions with VHDL to develop interoperable, reusable models. Only by adopting the standards and practices described in this book can the industry benefit and make system simulation feasible.

—Randy Harr, Sevni Technology

This book provides not only an excellent reference for those who write component models for board level verification, but also a much needed introduction to SDF and VITAL for timing simulation.

—Hardy Pottinger, University of Missouri-Rolla
 
 

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