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Intel Xeon Phi Coprocessor High-Performance Programming
 
 

Intel Xeon Phi Coprocessor High-Performance Programming, 1st Edition

 
Intel Xeon Phi Coprocessor High-Performance Programming, 1st Edition,James Jeffers,James Reinders,ISBN9780124104143
 
 
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Morgan Kaufmann

9780124104143

9780124104945

432

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Exploit the parallel power of the Intel Xeon Phi coprocessor for high-performance computing.

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Key Features

    • A practical guide to the essentials of the Intel Xeon Phi coprocessor
    • Presents best practices for portable, high-performance computing and a familiar and proven threaded, scalar-vector programming model
    • Includes simple but informative code examples that explain the unique aspects of this new highly parallel and high performance computational product
    • Covers wide vectors, many cores, many threads and high bandwidth cache/memory architecture

    Description

    Authors Jim Jeffers and James Reinders spent two years helping educate customers about the prototype and pre-production hardware before Intel introduced the first Intel Xeon Phi coprocessor. They have distilled their own experiences coupled with insights from many expert customers, Intel Field Engineers, Application Engineers and Technical Consulting Engineers, to create this authoritative first book on the essentials of programming for this new architecture and these new products.

    This book is useful even before you ever touch a system with an Intel Xeon Phi coprocessor. To ensure that your applications run at maximum efficiency, the authors emphasize key techniques for programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi coprocessors, or other high performance microprocessors. Applying these techniques will generally increase your program performance on any system, and better prepare you for Intel Xeon Phi coprocessors and the Intel MIC architecture.

    Readership

    Software engineers,  High Performance and Super Computing developers, scientific researchers in need of high-performance computing resources

    James Jeffers

    Jim Jeffers was the primary strategic planner and one of the first full-time employees on the program that became Intel ® MIC. He served as lead SW Engineering Manager on the program and formed and launched the SW development team. As the program evolved, he became the workloads (applications) and SW performance team manager. He has some of the deepest insight into the market, architecture and programming usages of the MIC product line. He has been a developer and development manager for embedded and high performance systems for close to 30 years.

    Affiliations and Expertise

    MIC Architecture Specialist, Intel

    James Reinders

    James Reinders is involved in multiple engineering, research and educational efforts to increase use of parallel programming throughout the industry. James has contributed to numerous projects including the world's first TeraFLOP/s supercomputer (ASCI Red) and the world's first TeraFLOP/s microprocessor (Intel® Xeon Phi™ coprocessor). James has authored numerous technical books, including three other books currently in print: Structured Parallel Programming (Morgan Kaufmann, 2012), Intel® Xeon Phi™ Coprocessor High Performance Programming (Morgan Kaufmann, 2013), and Multithreading for Visual Effects (2014).

    Affiliations and Expertise

    Director, Chief Evangelist, Intel Software, Intel Corporation, Portland, OR, USA

    View additional works by James Reinders

    Intel Xeon Phi Coprocessor High-Performance Programming, 1st Edition

    1. Introduction
    2. High Performance examples
    3. Benchmarking Apps
    4. Real-world Situations
    5. Lots of Data (Vectors)
    6. Lots of Tasks (not Threads)
    7. Processing Parallelism
    8. Coprocessor Architecture
    9. Coprocessor System Software
    10. Linux on the Coprocessor
    11. Math Library
    12. MPI
    13. Profiling
    14. Summary

    Quotes and reviews

    "Read this book. Authors Jim Jeffers and James Reinders spent two years helping educate customers about the prototype and pre-production hardware before Intel introduced the first Intel Xeon Phi coprocessor. They have distilled their own experiences coupled with insights from many expert customers, to create this authoritative first book on the essentials of programming for this new architecture and these new products."--Slashdot.org, May 5, 2013
    "The authors…are uniquely experienced in software development for this new silicon. As a result, this book is the definitive programming reference for the 60+ core monster from Intel…highly readable and interlaced with lots of code examples."--DrDobbs.com, April 2, 2013
    "This book belongs on the bookshelf of every HPC professional. Not only does it successfully and accessibly teach us how to use and obtain high performance on the Intel MIC architecture, it is about much more than that. It takes us back to the universal fundamentals of high-performance computing including how to think and reason about the performance of algorithms mapped to modern architectures, and it puts into your hands powerful tools that will be useful for years to come."
    Robert J. Harrison, Institute for Advanced Computational Science, Stony Brook University, from the Foreword
    "The book benefits software engineers, scientific researchers, and high performance and supercomputing developers in need of high-performance computing resources…"--HPCwire.com, March 31, 2013
    "The book benefits software engineers, scientific researchers, and high performance and supercomputing developers in need of high-performance computing resources…I got my hands on a preliminary copy of the book back in November at SC12, and I can tell you that Jim and James did a great job."--Knowledgespeak.com, April 1, 2013

     
     
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