Three-dimensional Integrated Circuit Design, 1st Edition

 
Three-dimensional Integrated Circuit Design, 1st Edition,Visileios Pavlidis,Eby Friedman,ISBN9780123743435
 
 
 

  &      

Morgan Kaufmann

9780123743435

9780080921860

336

235 X 191

Overcome Interconnect Bottleneck at the new frontier of Integrated Circuit Design: 3-Dimensions!

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Key Features

* Demonstrates how to overcome "interconnect bottleneck" with 3-D integrated circuit design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers
* The FIRST book on 3-D integrated circuit design...provides up-to-date information that is otherwise difficult to find
* Focuses on design issues key to the product development cycle...good design plays a major role in exploiting the implementation flexibilities offered in the 3-D
* Provides broad coverage of 3-D integrated circuit design, including interconnect prediction models, thermal management techniques, and timing optimization...offers practical view of designing 3-D circuits

Description

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elements has become the greatest determining factor in overall performance. 3-D integrated circuit design may offer the best solutions in the near future.

This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of 3-D integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of 3-D integrated circuits.

Readership

VLSI design engineers, CAD Designers of Microprocessors and Systems-on-Chip (SOC), concerned with 3-D integration in chip design...INTERCONNECT, at companies globally such as Microsoft, Honeywell, Intel, AMD, IBM, HP, NVIDIA, Marvell, Texas Instruments, Samsung, Hitachi, Sony, Fujitsu, Toshiba, ST Microelectronics, NXP, Freescale, Infineon, NOKIA, Qualcom, Cadence, Synopsys, Magma, Mentor Graphics, Tezzaron Inc, Ziptronix,
Tru-Si, IMEC Belgium, etc.

Visileios Pavlidis

Vasilis F. Pavlidis received the B.S. and M.Eng. in electrical and computer engineering from the Democritus University of Thrace, Xanthi, Greece, in 2000 and 2002, respectively. He received the M.Sc. and Ph.D. degrees from, University of Rochester, Rochester, NY in 2003 and 2008, respectively. From 2000 to 2002, he was with INTRACOM S.A., Athens, Greece. In summer of 2007, he was with Synopsys Inc., Mountain View, California. His current research interests are in the area of interconnect modeling, 3-D integration, networks-on-chip, and related design issues in VLSI.

Eby Friedman

Eby G. Friedman received the B.S. degree from Lafayette College in 1979, and the M.S. and Ph.D. degrees from the University of California, Irvine, in 1981 and 1989, respectively, all in electrical engineering. From 1979 to 1991, he was with Hughes Aircraft Company, rising to the position of manager of the Signal Processing Design and Test Department, responsible for the design and test of high performance digital and analog IC's. He has been with the Department of Electrical and Computer Engineering at the University of Rochester since 1991, where he is a Distinguished Professor, the Director of the High Performance VLSI/IC Design and Analysis Laboratory, and the Director of the Center for Electronic Imaging Systems. He is also a Visiting Professor at the Technion - Israel Institute of Technology. His current research and teaching interests are in high performance synchronous digital and mixed-signal microelectronic design and analysis with application to high speed portable processors and low power wireless communications. He is the author of more than 300 papers and book chapters, several patents, and the author or editor of ten books in the fields of high speed and low power CMOS design techniques, high speed interconnect, and the theory and application of synchronous clock and power distribution networks. He was the Editor-in-Chief of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, a Member of the editorial board of the Proceedings of the IEEE and a recipient of the University of Rochester Graduate Teaching Award, and a College of Engineering Teaching Excellence Award. Dr. Friedman is a Senior Fulbright Fellow and an IEEE Fellow.

Three-dimensional Integrated Circuit Design, 1st Edition

Chapter 1. Introduction
1.1. From the Integrated Circuit to the Computer
1.2. Interconnects; an old Friend
1.3. Three-Dimensional or Vertical Integration
1.3.1. Opportunities for Three-Dimensional Integration
1.3.2. Challenges for Three-Dimensional Integration
1.4. Book Organization
Chapter 2. Manufacturing of 3-D Packaged Systems
2.1. Three-Dimensional Integration
2.1.1. System-in-Package
2.1.2. Three-Dimensional Integrated Circuits
2.2. System-on-Package
2.3. Technologies for System-in-Package
2.3.1. Wire Bonded System-in-Package
2.3.2. Peripheral Vertical Interconnects
2.3.3. Area Array Vertical Interconnects
2.3.4. Metallizing the Walls of an SiP
2.4. Cost Issues for 3-D Integrated Systems
2.5. Summary
Chapter 3. 3-D Integrated Circuit Fabrication Technologies
3.1. Monolithic 3-D ICs
3.1.1. Stacked 3-D ICs
3.1.2. 3-D Fin-FETs
3.2. 3-D ICs with Through Silicon (TSV) or Interplane Vias
3.3. Contactless 3-D ICs
3.3.1. Capacitively Coupled 3-D ICs
3.3.2. Inductively Coupled 3-D ICs
3.4. Vertical Interconnects for 3-D ICs
3.4.1. Electrical Characteristics of Through Silicon Vias
3.5. Summary
Chapter 4. Interconnect Prediction Models
4.1. Interconnect Prediction Models for 2-D Circuits
4.2. Interconnect Prediction Models for 3-D ICs
4.3. Projections for 3-D ICs
4.4. Summary
Chapter 5. Physical Design Techniques for 3-D ICs
5.1. Floorplanning Techniques
5.1.1. Single versus Multi-Step Floorplanning for 3-D ICs
5.1.2. Multi-Objective Floorplanning Techniques for 3-D ICs
5.2. Placement Techniques
5.2.1. Multi-Objective Placement for 3-D ICs
5.3. Routing Techniques
5.4. Layout Tools
5.5. Summary
Chapter 6. Thermal Management Techniques
6.1. Thermal Analysis of 3-D ICs
6.1.1. Closed-Form Temperature Expressions
6.1.2. Compact Thermal Models
6.1.3. Mesh Based Thermal Models
6.2. Thermal Management Techniques without Thermal Vias
6.2.1. Thermal-Driven Floorplanning
6.2.2. Thermal-Driven Placement
6.3. Thermal Management Techniques Employing Thermal Vias
6.3.1. Region Constrained Thermal Via Insertion
6.3.2. Thermal Via Planning Techniques
6.3.3. Thermal Wire Insertion
6.4. Summary
Chapter 7. Timing Optimization for Two-Terminal Interconnects
7.1. Interplane Interconnect Models
7.2. Two-Terminal Nets with a Single Interplane Via
7.2.1. Elmore delay model of an interplane interconnect
7.2.2. Interplane Interconnect Delay
7.2.3. Optimum Via Location
7.2.4. Improvement in Interconnect Delay
7.3. Two-Terminal Interconnects with Multiple Interplane Vias
7.3.1. Two-Terminal Via Placement Heuristic
7.3.2. Two-Terminal Via Placement Algorithm
7.3.3. Application of the Via Placement Technique
7.4. Summary
Chapter 8. Timing Optimization for Multi-Terminal Interconnects
8.1. Timing-Driven Via Placement for Interplane Interconnect Trees
8.2. Multi-Terminal Interconnect Via Placement Heuristics
8.2.1. Interconnect Trees
8.2.2. Single Critical Sink Interconnect Trees
8.3. Via Placement Algorithms for Interconnect Trees
8.3.1. Interconnect Tree Via Placement Algorithm (ITVPA)
8.3.2. Single Critical Sink Interconnect Tree Via Placement Algorithm (SCSVPA)
8.4. Via Placement Results and Discussion
8.5. Summary
Appendix A:Enumeration of Gate Pairs in a 3-D IC
Appendix B:Formal Proof of Optimum Single Via Placement
Appendix C:Proof of the Two-Terminal Via Placement Heuristic
Appendix D:Proof of Condition for Via Placement of Multi-Terminal Nets
References
 
 
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