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ESL Design and Verification
 
 

ESL Design and Verification, 1st Edition

A Prescription for Electronic System Level Methodology

 
ESL Design and Verification, 1st Edition,Grant Martin,Brian Bailey,Andrew Piziali,ISBN9780080488837
 
 
 

  &      &      

Morgan Kaufmann

9780080488837

488

System-Level Design is offering competitive advantage in modern, system-on-chip design and this is THE authoritative reference!

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* Provides broad, comprehensive coverage not available in any other such book
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* Crammed full of state of the art content from notable industry experts

Description

Visit the authors' companion site! http://www.electronicsystemlevel.com/ - Includes interactive forum with the authors!

Electronic System Level (ESL) design has mainstreamed – it is now an established approach at most of the world’s leading system-on-chip (SoC) design companies and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with ‘no links to implementation’, ESL is evolving into a set of complementary methodologies that enable embedded system design, verification and debug through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems.

This book arises from experience the authors have gained from years of work as industry practitioners in the Electronic System Level design area; they have seen "SLD" or "ESL" go through many stages and false starts, and have observed that the shift in design methodologies to ESL is finally occurring. This is partly because of ESL technologies themselves are stabilizing on a useful set of languages being standardized (SystemC is the most notable), and use models are being identified that are beginning to get real adoption.

ESL DESIGN & VERIFICATION offers a true prescriptive guide to ESL that reviews its past and outlines the best practices of today.

Table of Contents
CHAPTER 1: WHAT IS ESL?
CHAPTER 2: TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL
CHAPTER 3: EVOLUTION OF ESL DEVELOPMENT
CHAPTER 4: WHAT ARE THE ENABLERS OF ESL?
CHAPTER 5: ESL FLOW
CHAPTER 6: SPECIFICATIONS AND MODELING
CHAPTER 7: PRE-PARTITIONING ANALYSIS
CHAPTER 8: PARTITIONING
CHAPTER 9: POST-PARTITIONING ANALYSIS AND DEBUG
CHAPTER 10: POST-PARTITIONING VERIFICATION
CHAPTER 11: HARDWARE IMPLEMENTATION
CHAPTER 12: SOFTWARE IMPLEMENTATION
CHAPTER 13: USE OF ESL FOR IMPLEMENTATION VERIFICATION
CHAPTER 14: RESEARCH, EMERGING AND FUTURE PROSPECTS
APPENDIX: LIST OF ACRONYMS

Readership

PRIMARY: Industry practitioners; SOC engineers designing embedded systems… System architect, (MP)SoC system designer, Engineering managers in the (MP)SoC system design field.

Grant Martin

Affiliations and Expertise

Tensilica, Inc., Pleasanton, CA

Brian Bailey

Affiliations and Expertise

Poseidon Design Systems, Oregon City, OR

Andrew Piziali

Affiliations and Expertise

Cadence Design Systems, Parker, TX

ESL Design and Verification, 1st Edition

CHAPTER 1 WHAT IS ESL?
So, What is ESL?
Who Should Read this Book
Chapter Listing
The Prescription
References
CHAPTER 2 TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL
Taxonomy
Introduction
Model Taxonomy
Temporal Axis
Data Axis
Functionality Axis
Structural Axis
ESL Taxonomy
Concurrency
Communication
Concurrency and Communications
Configurability
Examples
Languages
Processors
Flows
Definitions
Acronyms
CHAPTER 3 EVOLUTION OF ESL DEVELOPMENT
Introduction
Motivation for ESL Design
Traditional System Design Effectiveness
System Design with ESL Methodology
Behavioural Modelling Methodology
VSP: Potential Value
VSP: Programmer’s View
VSP: Programmer’s View Plus Timing
VSP: Cycle Accurate View
Behavioural Modelling Environments
Commercial Tools
The Trailblazer: VCC
Latest Generation Tools
POLIS
Ptolemy Simulator
SpecC Language
OSCI SystemC Reference Simulator
Historical Barriers to Adoption of Behavioural Modelling
The Demand Side
The Standards Barrier
Open SystemC Initiative
Open Core Protocol International Partnership
SpecC Technology Open Consortium
The System Level Language War
Automated Links to Chip Implementation
Automated Implementation of Fixed-Function Hardware
Commercial Tools
Mathematical Algorithm Development Tools
Graphical Algorithm Development Tools
The Trailblazer: Behavioral Compiler
Latest Generation High-Level Synthesis Tools
Open Source and Academic Tools
SPARK Parallelising High Level Synthesis (PHLS)
Automated Implementation of Programmable Hardware
Processor Design Using EDA Tools
Processor Designer and Chess/Checkers
CriticalBlue Cascade Coprocessor Synthesis
Processor Design Using IP-Based Methods
Configurable IP: Tensilica Xtensa and ARC 600/700
IP Assembly: ARM OptimoDE
Mainstreaming ESL Methodology
Who Bears the Risk?
Adoption by System Architects
Acceptance by RTL Teams
Behavioural Modelling IDEs
ASIP Processor Design
Effect of ESL on EDA Tool Seats
ESL and the Big 3 Three Companies
The Prescription
References
CHAPTER 4 WHAT ARE THE ENABLERS OF ESL?
Introduction
Tool and Model Landscape
System Designer Requirements
Accuracy
Time and Speed
Traffic Generator Models
Tool Cost and Value Proposition
Software Team Requirements
Accuracy
Register Accuracy
Cycle Count Accuracy
Concurrent and State Accuracy
Model Creation Time
Model Execution Performance
Tool Chain Cost
Hardware Team Requirements
Model Refinement
Verification Environment Provision
Verification
Verification Simulation
Cost
Who Will Service These Diverse Requirements?
Free or Open Source Software
F/OSS Community and Quality Effects
F/OSS Licenses
Copyright Ownership
License Terms
OSCI’s License
License Compatibility
The Scope of F/OSS Within ESL
Direct Benefits
Other Effects of F/OSS
Enabling (Academic) Research
Economics of F/OSS Business Models
Summary
References
CHAPTER 5 ESL FLOW
Introduction
Specifications and Modelling
Pre-Partitioning Analysis
Partitioning
Post-Partitioning Analysis and Debug
Post-Partitioning Verification
Hardware Implementation
Use of ESL for Implementation Verification
Provocative Thoughts
Summary
The Prescription
CHAPTER 6 SPECIFICATIONS AND MODELLING
Introduction
The Problem of Specification
The Implementation and Ambiguity Problems
The Heterogeneous Technology and Single-Source Problems
Architectures, Attributes and Behaviour
Formal and Executable Specifications and Modelling
Case Study: Requirements Management Process at Vandelay Industries
ESL Domains
Dataflow and Control flow
Protocol Stacks
Embedded Systems
Executable Specifications
Transaction Level Modelling and Executable Specifications
Executable Specifications and the Single-Source Problem
Some ESL Languages for Specification
MATLAB
Rosetta
SystemC
SystemVerilog
SDL
The UML
XML
Bluespec
Aspect Oriented Languages
Provocative Thoughts: Model Based Development
Model Driven Architecture
Software/Hardware Co-Design
Hardware
How to Use MDD
Summary
The Prescription
References
CHAPTER 7 PRE-PARTITIONING ANALYSIS
Introduction
Static Analysis of System Specifications
The Software Project Estimation Heritage—Function Point Analysis
Analysis of Hardware and Hardware-Dominated System Specifications
Traditional “ility” Analysis of Systems
Requirements Analysis
New Specification Methods – Rosetta
Conclusions on Static Analysis
The Role of Platform-Based ESL Design in Pre-Partitioning Analysis
Dynamic Analysis
Algorithmic Analysis
Commercial Tools for Algorithmic Analysis
Research Tools
Analysis Scenarios and Modelling
Example of Analysis of Signal Processing Algorithms
Filter Design Example
Complete System Specification to Silicon Methodology for Communications and Multimedia Signal Processing
Software Radio Example
How Much Analysis is Enough?
Downstream Use of Analysis Results
Case Study – JPEG Encoding
Summary and Provocative Thoughts
The Prescription for Pre-Partitioning Analysis
References
CHAPTER 8 PARTITIONING
Introduction
Functional Decomposition
Architecture Description
Platforms
Architectural Components
Modelling Levels
Partitioning
Refinement Based Methods
System Scheduling and Constraint Satisfaction
The Hardware Partition
Module Refinement
The Software Partition
Partitioning Over Multiple Processors
Partitioning over Multiple Tasks
Worst-Case Execution Time Analysis
The Operating System
Commercial Operating Systems
Custom Operating Systems
Memory Partitioning
Reconfigurable Computing
Reconfigurable Computing Architectures
Dynamic Online Partitioning
Communication Implementation
Interface Template Instantiation
Interface Synthesis
Provocative Thoughts
Summary
The Prescription
References
CHAPTER 9 POST-PARTITIONING ANALYSIS AND DEBUG
Introduction
Roles and Responsibilities
Hardware and Software Modelling and Co-Modelling
Single Model
Separate Model: Filtered/Translated
Separate Hosted Model
Modelling Infrastructure and Inter-Model Connections
Partitioned Systems and Re-Partitioning
Pre-Partitioned Model Components
Abstraction Levels
Standardising Abstraction Levels for Interoperability
Moving Between Abstraction Levels
Communication Specification
Dynamic and Static Analyses
Metrics and the Importance of Experience
Functional Analysis
Performance Analysis
Interface Analysis
Power Analysis
Area Analysis
Cost Analysis
Debug Capability Analysis
Observability
Controllability
Correctability
Provocative Thoughts
Summary
The Prescription
CHAPTER 10 POST-PARTITIONING ANALYSIS AND VERIFICATION
Introduction
Facets of Verification
Verification Planning
What is the Scope of the Verification Problem?
Specification Analysis
Bottom-Up Specification Analysis
Top-Down Specification Analysis
Coverage Model Top Level Design
Coverage Model Detailed Dsign
Hybrid Metric Coverage Models
What is the Solution to the Verification Problem?
Stimulus Generation
Response Checking
Verification Planning Automation
Verification Environment Implementation
Write
Verification
Environment
Failure Analysis
Coverage Analysis
Abstract Coverage
Other Approaches
Turning the Tables
Mutation Analysis
The Role of Prototyping
Platform Verification
Provocative Thoughts
Summary
The Prescription
CHAPTER 11 HARDWARE IMPLEMENTATION
Introduction
Extensible Processors
DSP Co-processors
Customised VLIW Co-Processors
Application Specific Co-Processors
High-level Hardware Design Flow for ASIC and FPGA
Behavioural Synthesis
Differences between RTL and Behavioural Code
Multicycle Functionality
Loops
Memory Access
Behavioural Synthesis Shortcomings: Input Language
Behavioural Synthesis Shortcomings: Timing
Behavioural Synthesis Shortcomings: Verification
ESL Synthesis
Language
Structure
Concurrency
Data types
Operations
Example
Input and Output
Verification
Timing
Scheduling
Allocation
Back-end Friendliness
Example Results
Hardware Design or Silver Bullet?
Role of Constraints
Pragmas
Code Changes
Example
Constraints
Code Modification
Design Exploration
Provocative Thoughts
Summary
The Prescription
References
CHAPTER 12 SOFTWARE IMPLEMENTATION
Introduction
Classical Software Development Methods for Embedded Systems and SoCs
Performance Estimation
Classical Development Tools
Developing Run-Time Software from ESL Models
UML Code Generation Case Study
Developing Software Using ESL Models as Run-Time Environments
Classes of ESL Models for Software Development
Observability for Debug and Analysis
Software Debug and Analysis Tools for Highly Observable Systems
Summary
Provocative Thoughts
The Prescription
References
CHAPTER 13 USE OF ESL FOR IMPLEMENTATION VERIFICATION
What This Chapter is Not About
Positive and Negative Verification
Verification Focus
Clear Box Verification
Verification IP
Dynamic Verification IP
Assertion Libraries
Properties and Assertions
Assertions
Formal Methods
Starting State
Limiting the Future
Speeding Up the Design
Limiting States
Coverage
System Verification
Post-Silicon Debug
Observability and Debug
Internal Logic Analyser
Dynamic Modifications
Provocative Thoughts
Sequential Equivalence Checking
Property-Based Design
Summary
The Prescription
CHAPTER 14 RESEARCH, EMERGING AND FUTURE PROSPECTS
Research
Metropolis
Space
Multiple Processors
Emerging Architectures
ROSES
Globalisation
Value Migration
Education
The Academic View
The Health of the Commercial EDA Industry
Summary
The Prescription
 
 
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