Verification Techniques for System-Level Design, 1st Edition,Masahiro Fujita,Indradeep Ghosh,Mukul Prasad,ISBN9780123706164
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Verification Techniques for System-Level Design, 1st Edition

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ISBN: 9780123706164

Pages: 256

Dimensions: 235 X 191

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Readership

PRIMARY: Practitioners/Researchers in System-Level Design and Verification; Design Engineers at companies such as Synopsis, Cadence, Intel.
SECONDARY: Reference for graduate-level courses in SoC design and verification.

Masahiro Fujita

*Spent 15 years at Fujitsu research laboratories. *Research on synthesis and verification of digital systems for more than 25 years *Full professor at VLSI Design and Education Center in the University of Tokyo

Affiliations and Expertise

Professor, VLSI Design & Education Center, University of Tokyo, Japan.

Indradeep Ghosh

Indradeep Ghosh received the Bachelor of Technology degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur, India, in 1993, and the M.A. and Ph.D. degrees in Electrical Engineering from Princeton University, Princeton, New Jersey, in 1995 and 1998, respectively. Since 1998 he has been a member of research staff in at Fujitsu Laboratories of America, Sunnyvale, California. He has authored or co-authored more that 40 technical articles in international journals and conferences and holds 6 US patents. He has given numerous presentations in international conferences and workshops. In Fujitsu he has been involved in design verification and testing of industrial systems that are currently in production. His research interests include testing, verification, and validation of hardware and software systems. He is senior member of the IEEE and a member of the ACM.

Affiliations and Expertise

Senior Researcher, Fujitsu Labs of America, Sunnyvale, CA, USA.

Mukul Prasad

Mukul Prasad: Mukul Prasad received the Bachelor of Technology degree in Electrical Engineering from the Indian Institute of Technology, Delhi, India, in 1995, and the Ph.D. degree in Electrical Engineering & Computer Sciences from the University of California at Berkeley in 2001. Since 2001 he has been a member of the research staff in the Trusted Systems Innovation group at Fujitsu Laboratories of America in Sunnyvale, California. His doctoral thesis and his subsequent research has involved the development and application of verification technologies such as Satisfiability solvers. His work has received a Best Paper Award at the Design Automation & Test in Europe Conference (DATE 2002). His current research addresses various problems in system-level design validation. He has co-authored more than 20 technical papers and presented three tutorials at international conferences and jointly holds 3 U.S. patents in the area of formal validation.

Affiliations and Expertise

Senior Researcher, Fujitsu Labs of America, Sunnyvale, CA, USA.

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Verification Techniques for System-Level Design
 
 

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